1. Field of the Invention
The field of invention relates to detecting misaligned electrical masks in the semiconductor manufacturing process. In particular, the field of invention relates to measuring alignment, rotation, and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation in devices defined by the mask layers.
2. Description of the Related Art
Semiconductor manufacturers produce a number of types of computer chips, including dynamic random access memory chips (DRAMs), microprocessors, application specific integrated circuits (ASICs), and digital signal processors, for example. Although the process for manufacturing these computer chips, also referred to as integrated circuits (IC), may vary depending on the type of chip, all include some fundamental manufacturing process steps such as deposition, photolithography, etching, ion implantation, polishing, cleaning, and drying, for example.
Often, throughout the semiconductor manufacturing process, repeated use is made of masks for creating multiple layers of circuit patterns on a chip. In particular, the process includes creating multiple layers (hereinafter “level”) by transferring a pattern from a mask to a light sensitive material, known in the art as a photoresist, on a substrate. In high yield semiconductor manufacturing processes it is especially crucial that the various mask levels that are transferred onto the photoresist be within specification such that it is aligned, without rotation, and without bias (i.e., oversized or undersized).
Typically, alignment is performed using physical techniques such as optical structures that are read by persons or read by pattern recognition software and tools using misalignment verniers, “box inside a box” optical reflection techniques or other manual comparative assessments. Although some masking levels result in structures that are still visible during the subsequent processing steps, many mask levels do not leave any visible physical structure behind. The most common of these are ion implant mask levels. Ion implantation is a materials engineering process whereby ions of a material can be implanted into the silicon wafer to change the physical properties of the silicon wafer. Often, for the ion implant mask levels, a layer of photoresist is applied, light is exposed through the mask, and subsequently developed to open the desired images. Next, this masked wafer is ion implanted, wherein the photoresist is used to control the areas where ions are implanted before the photoresist is chemically stripped away. Thus, the alignment of the ion implant mask is crucial in determining the areas that are implanted with ions, but difficult to determine through traditional techniques.
Current alignment measurement techniques suffer from several limitations. First, measurement of the alignment, rotation and bias of the mask often has to be done with the photoresist still in place since after the photoresist is removed there is no optically or electrically visible evidence remaining of the ion implant. Second, alternatives to physical alignment techniques, such as electrical alignment techniques fail to apply to lightly doped implants such as threshold tailoring implants, for example. Thus, there exists a need to measure the ion implant mask alignment, rotation, and bias of these masks after the wafers are fully processed and that apply to lightly doped implants.